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vhdl D触发器
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ddf1 IS
PORT
(
D,clk: IN STD_LOGIC;
Q: out STD_LOGIC
);
END ddf1;
ARCHITECTURE a1 OF ddf1 IS
BEGIN
signal sig_save: STD_LOGIC;
process(clk)
begin
if clk'event and clk='1' then
sig_save<=D;
end if;
Q<=sig_save;
end process;
END a1;
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