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vhdl表决器
-- MAX+plus II VHDL Template
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_ARITH.all;
USE ieee.std_logic_unsigned.all;
ENTITY maj IS
PORT( sw : in STD_LOGIC_vector(2 downto 0);
m : OUT STD_LOGIC );
END maj;
ARCHITECTURE concurrent OF maj IS
BEGIN
WITH sw SELECT
m<='1' WHEN "110",
'1' when "101",
'1' when "011",
'1' when "111",
'0' WHEN OTHERS;
END concurrent;
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