-- MAX+plus II VHDL Template

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_ARITH.all;
USE ieee.std_logic_unsigned.all;

entity addrdec is
port(
address : in std_logic_vector(15 downto 0);
cs1 : out std_logic;
cs2 : out std_logic

);
end entity addrdec;

architecture v1 of addrdec is
begin

cs1 <= '0' when
(address >= X"0000") and (address <= X"1FFF")
else '1';

cs2 <= '0' when
(address >= X"3100") and (address <= X"3FFF")
else '1';



end architecture v1;