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vhdl二分频
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity div2 is
PORT(CLK: IN STD_LOGIC;
CLK2: OUT STD_LOGIC);
end div2;
architecture fen of div2 is
signal temp:std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then
temp<=not temp;
end if;
end process;
clk2<=temp;
end fen;
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