-- MAX+plus II VHDL Template

LIBRARY ieee;
USE ieee.std_logic_1164.all;

-- MAX+plus II VHDL Example
-- Conditional Signal Assignment
-- Copyright (c) 1994 Altera Corporation

ENTITY mux2a IS
PORT
(
input0, input1, sel : IN BIT;
output : OUT BIT
);
END mux2a;

ARCHITECTURE maxpld OF mux2a IS
BEGIN

output <= input0 WHEN sel = '0' ELSE input1;

END maxpld;