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vhdl分频器
-- MAX+plus II VHDL Template
-- Clearable loadable enablable counter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY freq_div IS
PORT
(
clk : IN STD_LOGIC;
output : OUT STD_LOGIC
);
END freq_div;
ARCHITECTURE a OF freq_div IS
SIGNAL count_signal : INTEGER RANGE 0 TO 20000;
signal mid1 : STD_LOGIC ;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
if count_signal=19999 then
count_signal <= 0;
mid1<= not mid1;
else
count_signal <= count_signal + 1;
end if;
output <= mid1;
end if;
END PROCESS;
end a;
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