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vhdl计数器
-- MAX+plus II VHDL Template
-- Clearable loadable enablable counter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY counter60 IS
PORT
(
data_input : IN INTEGER RANGE 0 TO 63;
clk : IN STD_LOGIC;
ld_input : IN STD_LOGIC;
count_output : OUT INTEGER RANGE 0 to 63
);
END counter60;
ARCHITECTURE a OF counter60 IS
SIGNAL count_signal : INTEGER RANGE 0 TO 63;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ld_input = '1' THEN
count_signal <= data_input;
ELSE
if count_signal=59 then
count_signal <= 0;
else
count_signal <= count_signal + 1;
end if;
END IF;
end if;
count_output <= count_signal;
END PROCESS;
end a;
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