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vhdl寄存器
-- MAX+plus II VHDL Example
-- User-Defined Macrofunction
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg8 IS
PORT(
d : IN BIT_VECTOR(11 DOWNTO 0);
clk : IN BIT;
q : OUT BIT_VECTOR(11 DOWNTO 0));
END reg8;
ARCHITECTURE a OF reg8 IS
BEGIN
PROCESS(clk)
BEGIN
if clk'event and clk='1' then
q <= d;
end if;
END PROCESS;
END a;
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