LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;

ENTITY adder4b IS
PORT
(
cin: IN std_logic;
a,b: IN std_logic_vector(3 downto 0);
s: out std_logic_vector(3 downto 0);
cout: OUT std_logic
);
END adder4b;

ARCHITECTURE rtl OF adder4b IS
signal sint: std_logic_vector(4 downto 0);
signal aa,bb: std_logic_vector(4 downto 0);
BEGIN

aa<='0'&A; bb<='0'&b;
sint<=aa+bb+cin;
s<=sint(3 downto 0);
cout <= sint(4);

END rtl;