-- MAX+plus II VHDL Template

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_ARITH.all;
USE ieee.std_logic_unsigned.all;

ENTITY seg7dec_1 IS

PORT
(
num: IN STD_LOGIC_VECTOR(3 downto 0);
dout: out STD_LOGIC_VECTOR(6 downto 0)

);

END seg7dec_1;

ARCHITECTURE a1 OF seg7dec_1 IS

BEGIN

with num select

DOUT<="1111110" when "0000",
"0110000" when "0001",
"1101101" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1111011" when "1001",
"0000000" when others;

END a1;