-- MAX+plus II VHDL Template

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_ARITH.all;
USE ieee.std_logic_unsigned.all;

entity HCT245 is
port(A, B : inout std_logic_vector(7 downto 0);
DIR, G : in std_logic);
end HCT245;

architecture VER1 of HCT245 is
begin
A <= B when (G = '0') and (DIR = '0') else (others => 'Z');
B <= A when (G = '0') and (DIR = '1') else (others => 'Z');
end VER1;