-- MAX+plus II VHDL Template

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mux4a_1 IS

PORT
(
d0,d1,d2,d3,a,b : IN STD_LOGIC;
q: out STD_LOGIC
);

END mux4a_1;

ARCHITECTURE a1 OF mux4a_1 IS

signal sel: integer range 0 to 4;

BEGIN

sel<=0 when a='0' and b='0' else
1 when a='1' and b='0' else
2 when a='0' and b='1' else
3 when a='1' and b='1' else
4;

with sel select
q<= d0 when 0,
d1 when 1,
d2 when 2,
d3 when 3,
'0' when others;

END a1;