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vhdl同步D触发器
-- MAX+plus II VHDL Template
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff2 IS
PORT
(
D,clk,clr: IN STD_LOGIC;
Q: out STD_LOGIC
);
END dff2;
ARCHITECTURE a1 OF dff2 IS
BEGIN
process(clk,D,clr)
begin
if clk'event and clk='1' then
if clr='1' then
Q<='1';
else
Q<=D;
end if;
end if;
end process;
END a1;
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