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vhdl伪随机码m序列发生器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ps4 is
PORT(CLK,load: IN STD_LOGIC;
q: OUT STD_LOGIC);
end ps4;
architecture a1 of ps4 is
signal c0,c1,c2,c3:std_logic;
begin
process(clk,load)
begin
if clk'event and clk='1' then
if(load='1') then
c0<='1';
c1<='0';
c2<='0';
c3<='0';
q<=c3;
else
c1<=c0;
c2<=c1;
c3<=c2;
c0<=c3 xor c1;
q<=c3;
end if;
end if;
end process;
end a1;
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